Principal Design Engineer

  • At least 15 years industry experience, with 10 years work experience in board level and ASIC/FPGA product definition, design and development.
  • Proven experience in design, development and testing of one or more commercial ASICs for ATM-based MPLS LER/LSR, IP routers, and/or ATM switches.
  • Innovation in specification of ASIC functionality, architectures (algorithms, data structures, circuit design), and partitioning for routers/switches.
  • Knowledge of hardware tradeoffs for ASIC design including die size, feature size, power dissipation, pin bandwidth (LVDS, high-speed serial links), and packaging technology.
  • Background in Layers 1 through 7 Network processing functionality, such as those existing in the line interface (service) cards and switching fabrics.
  • In-depth knowledge of communications (IP, ATM, and MPLS) protocols.
  • Experience developing project plans and milestones.
  • High proficiency with tools (Cadence, Synopsys), vendors (ASIC, Fabrication), and services (ASIC, FPGA) related to ASIC/FPGA development.


December 21, 2002