Senior Design Engineer

  • At least 10 years industry experience, with 7 years work experience in board level and ASIC/FPGA product definition, design and development.
  • Experience in design, development and test of commercial ASICs for ATM-based MPLS LER/LSR, IP routers, and/or ATM switches.
  • Experience in developing specification of ASIC functionality, architectures (algorithms, data structures, circuit design), and partitioning for routers/switches.
  • Familiarity with hardware tradeoffs for ASIC design including die size, feature size, power dissipation, pin bandwidth (LVDS, high-speed serial links), and packaging technology.
  • Background in Layers 1 through 7 Network processing functionality such as those existing in the line interface (service) cards and switching fabrics.
  • Knowledge of communications (IP, ATM, and MPLS) protocols.
  • Familiarity with project milestones and team environment.
  • Proficiency with tools (Cadence, Synopsys), vendors (ASIC, Fabrication), and services (ASIC, FPGA) related to ASIC/FPGA development.

|back|

           
December 21, 2002